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8-/10-/12-/14-bit high bandwidth multiplying dacs with serial interface ad5450/ad5451/ad5452/ad5453 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2011 analog devices, inc. all rights reserved. features 12 mhz multiplying bandwidth inl of 0.25 lsb @ 8-bit 8-lead tsot and msop packages 2.5 v to 5.5 v supply operation pin-compatible 8-/10-/12-/14-bit current output dacs 10 v reference input 50 mhz serial interface 2.7 msps update rate extended temperature range: C40c to +125c 4-quadrant multiplication power-on reset with brownout detect <0.4 a typical current consumption guaranteed monotonic qualified for automotive applications applications portable battery-powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming functional block diagram 04587-001 8-/10-/12-/14-bit ref r-2r dac dac register input latch power-on reset control logic and input shift register r i out 1 r fb v dd v ref gnd sdin sclk sync ad5450/ ad5451/ ad5452/ ad5453 figure 1. general description the ad5450/ad5451/ad5452/ad5453 1 are cmos 8-/10-/ 12-/14-bit current output digital-to-analog converters, respectively. these devices operate from a 2.5 v to 5.5 v power supply, making them suited to several applications, including battery-powered applications. as a result of manufacture on a cmos submicron process, these dacs offer excellent 4-quadrant multiplication characteristics of up to 12 mhz. these dacs utilize a double-buffered, 3-wire serial interface that is compatible with spi?, qspi?, microwire?, and most dsp interface standards. upon power-up, the internal shift register and latches are filled with 0s, and the dac output is at zero scale. the applied external reference input voltage (v ref ) determines the full-scale output current. these parts can handle 10 v inputs on the reference, despite operating from a single-supply power supply of 2.5 v to 5.5 v. an integrated feedback resistor (r fb ) provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier. the ad5450/ad5451/ad5452/ad5453 dacs are available in small 8-lead tsot, and the ad5452/ad5453 are also available in msop packages. the ad5453 also comes in 8-lead lfcsp. 1 u.s. patent number 5,689,257.
ad5450/ad5451/ad5452/ad5453 rev. e | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 15 general description ....................................................................... 16 dac section................................................................................ 16 circuit operation ....................................................................... 16 single-supply applications ....................................................... 18 adding gain................................................................................ 18 divider or programmable gain element ................................ 19 reference selection .................................................................... 19 amplifier selection .................................................................... 19 serial interface ............................................................................ 21 microprocessor interfacing....................................................... 22 pcb layout and power supply decoupling ........................... 24 evaluation board for the dac...................................................... 25 power supplies for the evaluation board................................ 25 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 29 automotive products ................................................................. 29 revision history 3/11rev. d to rev. e changes to sync function section ............................................ 21 added figure 54 (renumbered sequentially) ............................ 21 added figure 55 and table 11 ..................................................... 22 2/11rev. c to rev. d added 8-lead lfcsp.........................................................universal changes to features section............................................................ 1 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 added automotive products section .......................................... 28 1/10rev. b to rev. c changes to dac control bits c1, c0.......................................... 21 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 3/06rev. a to rev. b updated format..................................................................universal changes to features ..........................................................................1 changes to general description .....................................................1 changes to specifications.................................................................4 changes to figure 27 and figure 28............................................. 11 change to table 9 ........................................................................... 20 changes to table 12 ....................................................................... 26 updated outline dimensions....................................................... 27 changes to ordering guide .......................................................... 28 7/05rev. 0 to rev. a added ad5453 ...................................................................universal changes to specifications.................................................................4 change to figure 21 ....................................................................... 10 updated outline dimensions....................................................... 27 changes to ordering guide .......................................................... 28 1/05revision 0: initial version
ad5450/ad5451/ad5452/ad5453 rev. e | page 3 of 32 specifications v dd = 2.5 v to 5.5 v, v ref = 10 v. temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. dc performance measured with op177 and ac performance measured with ad8038, unless otherwise noted. table 1. parameter min typ max unit conditions static performance ad5450 resolution 8 bits relative accuracy 0.25 lsb differential nonlinearity 0.5 lsb guaranteed monotonic total unadjusted error 0.5 lsb gain error 0.25 lsb ad5451 resolution 10 bits relative accuracy 0.25 lsb differential nonlinearity 0.5 lsb guaranteed monotonic total unadjusted error 0.5 lsb gain error 0.25 lsb ad5452 resolution 12 bits relative accuracy 0.5 lsb differential nonlinearity 1 lsb guaranteed monotonic total unadjusted error 1 lsb gain error 0.5 lsb ad5453 resolution 14 bits relative accuracy 2 lsb differential nonlinearity ?1/+2 lsb guaranteed monotonic total unadjusted error 4 lsb gain error 2.5 lsb gain error temperature coefficient 1 2 ppm fsr/c output leakage current 1 na data = 0x0000, t a = 25c, i out 1 10 na data = 0x0000, t a = ?40c to +125c, i out 1 reference input 1 reference input range 10 v v ref input resistance 7 9 11 k input resistance, tc = ?50 ppm/c r fb feedback resistance 7 9 11 k input resistance, tc = ?50 ppm/c input capacitance zero-scale code 18 22 pf full-scale code 18 22 pf digital inputs/outputs 1 input high voltage, v ih 2.0 v v dd = 3.6 v to 5 v 1.7 v v dd = 2.5 v to 3.6 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 na t a = 25c 10 na t a = ?40c to +125c input capacitance 10 pf
ad5450/ad5451/ad5452/ad5453 rev. e | page 4 of 32 parameter min typ max unit conditions dynamic performance 1 reference-multiplying bw 12 mhz v ref = 3.5 v, dac loaded with all 1s multiplying feedthrough error v ref = 3.5 v, dac loaded with all 0s 72 db 100 khz 64 db 1 mhz 44 db 10 mhz output voltage settling time v ref = 10 v, r load = 100 ; dac latch alternately loaded with 0s and 1s measured to 1 mv of fs 100 110 ns measured to 4 mv of fs 24 40 ns measured to 16 mv of fs 16 33 ns digital delay 20 40 ns interface delay time 10% to 90% settling time 10 30 ns rise and fall times, v ref = 10 v, r load = 100 digital-to-analog glitch impulse 2 nv-s 1 lsb change around major carry, v ref = 0 v output capacitance i out 1 13 pf dac latches loaded with all 0s 28 pf dac latches loaded with all 1s i out 2 18 pf dac latches loaded with all 0s 5 pf dac latches loaded with all 1s digital feedthrough 0.5 nv-s feedthrough to dac output with cs high and alternate loading of all 0s and all 1s analog thd 83 db v ref = 3.5 v p-p, all 1s loaded, f = 1 khz digital thd clock = 1 mhz, v ref = 3.5 v 50 khz f out 71 db 20 khz f out 77 db output noise spectral density 25 nv/hz @ 1 khz sfdr performance (wide band) clock = 1 mhz, v ref = 3.5 v 50 khz f out 78 db 20 khz f out 74 db sfdr performance (narrow band) clock = 1 mhz, v ref = 3.5 v 50 khz f out 87 db 20 khz f out 85 db intermodulation distortion 79 db f 1 = 20 khz, f 2 = 25 khz, clock = 1 mhz, v ref = 3.5 v power requirements power supply range 2.5 5.5 v i dd 0.4 10 a t a = ?40c to +125c, logic inputs = 0 v or v dd 0.6 a t a = 25c, logic inputs = 0 v or v dd power supply sensitivity 1 0.001 %/% ?v dd = 5% 1 guaranteed by design and characterization, not subject to production test.
ad5450/ad5451/ad5452/ad5453 rev. e | page 5 of 32 timing characteristics all input signals are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. table 2. parameter 1 v dd = 2.5 v to 5.5 v unit conditions/comments f sclk 50 mhz max maximum clock frequency t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 8 ns min sync falling edge to sclk active edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 5 ns min sync rising edge to sclk active edge t 8 30 ns min minimum sync high time update rate 2.7 msps consists of cycle time, sync high time, data setup, and output voltage settling time 1 guaranteed by design and characterization, not subject to production test. 04587-002 sclk sync din db15 db0 t 7 t 3 t 2 t 6 t 5 t 4 t 8 t 1 figure 2. timing diagram
ad5450/ad5451/ad5452/ad5453 rev. e | page 6 of 32 absolute maximum ratings transient currents of up to 100 ma do not cause scr latch-up. t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +7 v v ref , r fb to gnd ?12 v to +12 v i out 1 to gnd ?0.3 v to +7 v input current to any pin except supplies 10 ma logic inputs and output 1 ?0.3 v to v dd + 0.3 v operating temperature range, extended (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 8-lead msop 206c/w 8-lead tsot 211c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c 1 overvoltages at sclk, sync , and sdin are clamped by internal diodes. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5450/ad5451/ad5452/ad5453 rev. e | page 7 of 32 pin configurations and function descriptions 04587-003 ad5450/ ad5451/ ad5452/ ad5453 r fb 1 v ref 2 v dd 3 sync 4 i out 1 gnd sclk sdin 8 7 6 5 figure 3. 8-lead tsot pin configuration 04587-004 ad5452/ ad5453 i out 1 1 gnd 2 sclk 3 sdin 4 r fb v ref v dd sync 8 7 6 5 figure 4. 8-lead msop pin configuration notes 1. the exposed pad must be connected to ground. top view (not to scale) ad5453 3 sclk 4 sdin 1i out 1 2 gnd 6v dd 5sync 8r fb 7v ref 04587-205 figure 5. 8-lead lfcsp pin configuration table 4. pin function descriptions pin no 1 tsot msop lfcsp mnemonic description 1 8 8 r fb dac feedback resistor. establish voltage outp ut for the dac by connecting to external amplifier output. 2 7 7 v ref dac reference voltage input. 3 6 6 v dd positive power supply input. these parts ca n operate from a supply of 2.5 v to 5.5 v. 4 5 5 sync active low control input. this is the frame sync hronization signal for th e input data. data is loaded to the shift register upon the active edge of the following clocks. 5 4 4 sdin serial data input. data is clocke d into the 16-bit input register upon the active edge of the serial clock input. by default, in power- up mode data is clocked into the shift register upon the falling edge of sclk. the control bits allow the user to change the active edge to a rising edge. 6 3 3 sclk serial clock input. by de fault, data is clocked into the input shift register upon the falling edge of the serial clock input. alternatively, by mean s of the serial control bits, the device can be configured such that data is clocked into the shift register upon the rising edge of sclk. 7 2 2 gnd ground pin. 8 1 1 i out 1 dac current output. n/a n/a epad epad exposed pad must be connected to ground. 1 n/a = not applicable.
ad5450/ad5451/ad5452/ad5453 rev. e | page 8 of 32 typical performance characteristics 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 256 04587-020 code inl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 6. inl vs. code (8-bit dac) 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 128 256 384 512 640 768 896 1024 04587-021 code inl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 7. inl vs. code (10-bit dac) 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 512 1024 1536 2048 2560 3072 2584 4096 04587-022 code inl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 8. inl vs. code (12-bit dac) 2.0 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 0 2048 4096 6144 8192 10240 12288 14336 16384 04587-023 code inl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 9. inl vs. code (14-bit dac) 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 32 64 96 128 160 192 224 256 04587-024 code dnl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 10. dnl vs. code (8-bit dac) 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 128 256 384 512 640 768 896 1024 04587-025 code dnl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 11. dnl vs. code (10-bit dac)
ad5450/ad5451/ad5452/ad5453 rev. e | page 9 of 32 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 2584 4096 04587-026 code dnl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 12. dnl vs. code (12-bit dac) 2.0 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 0 2048 4096 6144 8192 10240 12288 14336 16384 04587-027 code dnl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 13. dnl vs. code (14-bit dac) ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 2345678910 reference voltage (v) inl (lsb) t a = 25 c v dd = 5v ad5452 04587-070 max inl min inl figure 14. inl vs. reference voltage ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2345678910 reference voltage (v) dnl (lsb) t a = 25 c v dd = 5v ad5452 04587-071 max dnl min dnl figure 15. dnl vs. reference voltage 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 32 64 96 128 160 192 224 256 04587-030 code tue (lsb) t a = 25 c v ref = 10v v dd = 5v ad5450 figure 16. tue vs. code (8-bit dac) 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 128 256 384 512 640 768 896 1024 04587-031 code tue (lsb) t a = 25 c v ref = 10v v dd = 5v ad5451 figure 17. tue vs. code (10-bit dac)
ad5450/ad5451/ad5452/ad5453 rev. e | page 10 of 32 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 2584 4096 04587-032 code tue (lsb) t a = 25 c v ref = 10v v dd = 5v figure 18. tue vs. code (12-bit dac) 2.0 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 0 2048 4096 6144 8192 10240 12288 14336 16384 04587-033 code inl (lsb) t a = 25 c v ref = 10v v dd = 5v figure 19. tue vs. code (14-bit dac) ?2.0 ?1.5 ?1.0 0 1.0 1.5 2.0 2345 8910 reference voltage (v) tue (lsb) 04587-072 76 max tue ?0.5 0.5 t a = 25c v dd = 5v ad5452 min tue figure 20. tue vs. reference voltage ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?60 ?40 ?20 0 60 80 100 120 140 temperature (c) gain error (lsb) 04587-073 4020 v dd = 5v v dd = 3v figure 21. gain error (lsb) vs. temperature ?2.0 ?1.5 ?1.0 0 1.0 1.5 2.0 2345 8910 reference voltage (v) gain error (lsb) 04587-074 76 ?0.5 0.5 t a = 25 c v dd = 5v ad5452 figure 22. gain error (lsb) vs. reference voltage 2.0 1.6 1.2 0.8 0.4 0 ?40 ?20 0 20 40 60 80 100 120 04587-039 temperature (c) i out 1 leakage (na) i out 1 v dd = 5v i out 1v dd = 3v figure 23. i out 1 leakage current vs. temperature
ad5450/ad5451/ad5452/ad5453 rev. e | page 11 of 32 2.5 2.0 1.5 1.0 0.5 0 012345 04587-038 input voltage (v) current (ma) t a = 25 c v dd = 3v v dd = 5v figure 24. supply current vs. logic input voltage 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 ?40 ?20 0 20 40 60 80 100 120 04587-037 temperature ( c) current ( a) v dd = 5v v dd = 3v all 1s all 0s figure 25. supply current vs. temperature 04587-075 1 10 100 1k 10k 100k 1m 10m frequency (hz) 6 0 1 2 3 4 5 current (ma) t a = 25c ad5452 loading 010101010101 v dd = 5v v dd = 3v figure 26. supply current vs. update rate 2.5 5.5 voltage (v) 1.8 1.2 1.0 0.4 0.2 0 v ih 04587-076 1.6 1.4 0.8 0.6 3.0 3.5 4.5 4.0 5.0 v il threshold voltage (v) t a = 25 c figure 27. threshold voltage vs. supply voltage 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 100k 1m 10m 100m gain (db) frequency (hz) 04587-108 all on db11 db10 db9 db8 db6 db5 db4 db3 db7 db2 db12 db13 v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier t a = 25c loading zs to fs figure 28. reference multiplying bandwidth vs. frequency and code 0.6 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 10k 100k 1m 10m 100m gain (db) frequency (hz) 04587-109 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier figure 29. reference multiplying bandwidthall 1s loaded
ad5450/ad5451/ad5452/ad5453 rev. e | page 12 of 32 04587-079 10k 100k 1m 10m 100m frequency (hz) 3 ?9 0 gain (db) t a = 25c v dd = 5v ?6 ?3 v ref = 2v, ad8038 c comp = 1pf v ref = 2v, ad8038 c comp = 1.5pf v ref = 15v, ad8038 c comp = 1pf v ref = 15v, ad8038 c comp = 1.5pf v ref = 15v, ad8038 c comp = 1.8pf figure 30. reference multiplying bandwidth vs. frequency and compensation capacitor 04587-080 50 200 225 250 time (ns) 0.08 ?0.06 output voltage (v) ?0.02 175 100 125 150 75 0.06 0.04 0.02 0 ?0.04 t a = 25 c v dd = 0v ad8038 amplifier c comp = 1.8pf v dd =5v 0x7ff to 0x800 nrg = 2.154nvs v dd = 3v 0x7ff to 0x800 nrg = 1.794nvs v dd =5v 0x800 to 0x7ff nrg = 0.694nvs v dd =5v 0x800 to 0x7ff nrg = 0.694nvs figure 31. midscale transition, v ref = 0 v 50 200 225 250 time (ns) ?1.66 ?1.80 output voltage (v) ?1.76 175 100 125 150 75 ?1.68 ?1.70 ?1.72 ?1.74 ?1.78 t a = 25 c v dd = 3.5v ad8038 amplifier c comp = 1.8pf v dd =5v 0x7ff to 0x800 nrg = 2.154nvs v dd = 3v 0x7ff to 0x800 nrg = 1.794nvs v dd =5v 0x800 to 0x7ff nrg = 0.694nvs v dd =5v 0x800 to 0x7ff nrg = 0.694nvs 04587-081 figure 32. midscale transition, v ref = 3.5 v 04587-082 1 10 100 1k 10k 100k 1m 10m frequency (hz) 10 ?100 ?90 ?70 ?50 ?30 ?10 psrr (db) t a = 25 c v dd = 3v ad8038 amplifier ?80 ?60 ?40 ?20 0 full scale zero scale figure 33. power supply rejection ratio vs. frequency 04587-083 thd+n(db) t a = 25c v dd = 5v v ref = 3.5v 100 1k 10k 100k frequency (hz) ? 60 ?90 ?85 ?75 ?65 ?80 ?70 figure 34. thd + noise vs. frequency 04587-084 05 f out (khz) 100 0 sfd 0 r (db) 40 20 30 40 10 80 60 20 t a = 25c v ref = 3.5v ad8038 amplifier mclk = 500khz mclk = 1mhz mclk = 200khz figure 35. wideband sfdr vs. f out frequency
ad5450/ad5451/ad5452/ad5453 rev. e | page 13 of 32 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500k t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier frequency (hz) 400k 300k 200k 100k sfdr (db) 04587-085 figure 36. wideband sfdr, f out = 20 khz, clock = 1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 500k frequency (hz) 400k 300k 200k 100k sfdr (db) 04587-086 t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier figure 37. wideband sfdr, f out = 50 khz, clock = 1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 10k 30k frequency (hz) 25k 20k 15k sfdr (db) 04587-087 t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier figure 38. narrow-band sfdr, f out = 20 khz, clock = 1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 30k 70k t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier frequency (hz) 60k 50k 40k sfdr (db) 04587-088 figure 39. narrow-band sfdr , f out = 50 khz, clock = 1 mhz
ad5450/ad5451/ad5452/ad5453 rev. e | page 14 of 32 ?100 ?90 ?80 ?60 ?40 ?20 0 10k 35k frequency (hz) 30k 25k 20k 15k imd (db) 04587-089 ?70 ?50 ?30 ?10 t a = 25 c v ref = 3.5v ad8038 amplifier figure 40. narrow-band imd, f out = 20 khz, 25 khz, clock = 1 mhz ?100 ?90 ?80 ?60 ?40 ?20 0 0 500k t a = 25 c v ref = 3.5v ad8038 amplifier frequency (hz) 400k 300k 200k 100k imd (db) 04587-090 ?70 ?50 ?30 ?10 figure 41. wideband imd, f out = 20 khz, 25 khz, clock = 1 mhz 04587-091 100 1k 10k 100k 1m frequency (hz) 80 0 70 50 60 40 20 30 10 full scale loaded to dac midscale loaded to dac zero scale loaded to dac output noise (nv/ hz) t a = 25 c ad8038 amplifier figure 42. output noise spectral density
ad5450/ad5451/ad5452/ad5453 rev. e | page 15 of 32 terminology relative accuracy (endpoint nonlinearity) a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is mea- sured after adjusting for zero and full scale and is normally expressed in lsbs or as a percentage of the full-scale reading. differential nonlinearity the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temperature range ensures monotonicity. gain error (full-scale error) a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref ? 1 lsb. gain error of the dacs is adjustable to zero with external resistance. output leakage current the current that flows into the dac ladder switches when it is turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. output capacitance capacitance from i out 1 to agnd. output current settling time the amount of time it takes for the output to settle to a specified level for a full-scale input change. for these devices, it is specified with a 100 resistor to ground. the settling time specification includes the digital delay from the sync rising edge to the full- scale output change. digital-to-analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-s or nv-s, depending on whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs may be capacitively coupled through the device and produce noise on the i out pins. this noise is coupled from the outputs of the device onto follow-on circuitry. this noise is digital feedthrough. multiplying feedthrough error the error due to capacitive feedthrough from the dac reference input to the dac i out 1 terminal when all 0s are loaded to the dac. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower-order harmonics, such as second to fifth, are included. 1 5432 v vvvv thd 2222 log20 +++ = digital intermodulation distortion (imd) second-order intermodulation measurements are the relative magnitudes of the fa and fb tones generated digitally by the dac and the second-order products at 2fa ? fb and 2fb ? fa. compliance voltage range the maximum range of (output) terminal voltage for which the device provides the specified characteristics. spurious-free dynamic range (sfdr) the usable dynamic range of a dac before spurious noise interferes or distorts the fundamental signal. sfdr is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full nyquist bandwidth (half the dac sampling rate or f s /2). narrow-band sfdr is a measure of sfdr over an arbitrary window size, in this case 50% of the fundamental. digital sfdr is a measure of the usable dynamic range of the dac when the signal is a digitally generated sine wave.
ad5450/ad5451/ad5452/ad5453 rev. e | page 16 of 32 general description dac section the ad5450/ad5451/ad5452/ad5453 are 8-/10-/12-/14-bit current output dacs, respectively, consisting of a segmented (4-bit) inverting r-2r ladder configuration. a simplified diagram for the 12-bit ad5452 is shown in figure 43 . 2r s1 2r s2 2r s3 2r s12 2r dac data latches and drivers r r fb i out 1 v ref 04587-060 rr r agnd figure 43. ad5452 simplified ladder the feedback resistor, r fb , has a value of r. the value of r is typically 9 k (with a minimum value of 7 k and a maximum value of 11 k). if i out 1 is kept at the same potential as gnd, a constant current flows in each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref is always constant and nominally of value r. the dac output (i out 1) is code-dependent, producing various resistances and capacitances. when choosing the external amplifier, take into account the variation in impedance generated by the dac on the amplifiers inverting input node. access is provided to the v ref , r fb , and i out 1 terminals of the dac, making the device extremely versatile and allowing it to be configured in several operating modes; for example, it can provide a unipolar output or can provide 4-quadrant multiplication in bipolar mode. note that a matching switch is used in series with the internal r fb feedback resistor. if users attempt to measure r fb , power must be applied to v dd to achieve continuity. circuit operation unipolar mode using a single op amp, these devices can easily be configured to provide a 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 44 . when an output amplifier is connected in unipolar mode, the output voltage is given by ref n out v d v ?= 2 where: d is the fractional representation of the digital word loaded to the dac. d = 0 to 255 (8-bit ad5450). = 0 to 1023 (10-bit ad5451). = 0 to 4095 (12-bit ad5452). = 0 to 16,383 (14-bit ad5453). n is the number of bits. note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. 04587-009 r fb i out 1 gnd sclk sdin v ref v ref r1 sync ad5450/ ad5451/ ad5452/ ad5453 v dd v dd agnd c1 a1 r2 v out = 0 to ?v ref controller notes 1. r1 and r2 used only if gain adjustment is required. 2 . c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 44. unipolar mode operation these dacs are designed to operate with either negative or positive reference voltages. the v dd power pin is only used by the internal digital logic to drive the on and off states of the dac switches. these dacs are designed to accommodate ac reference input signals in the range of ?10 v to +10 v. with a fixed 10 v reference, the circuit shown in figure 44 gives a unipolar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table 5 shows the relationship between the digital code and the expected output voltage for a unipolar operation using the 8-bit ad5450. table 5. unipolar code table for the ad5450 digital input analog output (v) 1111 1111 ?v ref (255/256) 1000 0000 ?v ref (128/256) = ?v ref /2 0000 0001 ?v ref (1/256) 0000 0000 ?v ref (0/256) = 0
ad5450/ad5451/ad5452/ad5453 rev. e | page 17 of 32 bipolar mode in some applications, it may be necessary to generate a full 4-quadrant multiplying operation or a bipolar output swing. this can be easily accomplished by using another external amplifier and some external resistors, as shown in figure 45 . in this circuit, the second amplifier, a2, provides a gain of 2. biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. the transfer function of this circuit shows that both negative and positive output voltages are created as the input data (d) is incremented from code 0 (v out = ? v ref ) to midscale (v out ? 0 v ) to full scale (v out = +v ref ). ref n ref out v d vv ? ? ? ? ? ? ? = ? 1 2 where: d is the fractional representation of the digital word loaded to the dac. d = 0 to 255 (8-bit ad5450). = 0 to 1023 (10-bit ad5451). = 0 to 4095 (12-bit ad5452). n is the resolution of the dac. when v in is an ac signal, the circuit performs 4-quadrant multiplication. table 6 shows the relationship between the digital code and the expected output voltage for a bipolar operation using the 8-bit ad5450. table 6. bipolar code table for the ad5450 digital input analog output (v) 1111 1111 +v ref (127/128) 1000 0000 0 0000 0001 ?v ref (127/128) 0000 0000 ?v ref (128/128) 04587-010 notes 1. r1 and r2 used only if gain adjustment is required. adjust r1 for v out = 0v with code 10000000 loaded to dac. 2. matching and tracking is essential for resistor pairs r3 and r4. 3. c1 phase compensation (1pf to 2pf) may be required if a1/a2 is a high speed amplifier. r fb i out 1 gnd sclk sdin v ref 10v v ref r1 sync ad5450/ ad5451/ ad5452/ ad5453 v dd v dd agnd c1 a1 a2 r2 v out = ?v ref to +v ref controller r3 20k ? r4 10k ? r5 20k ?
ad5450/ad5451/ad5452/ad5453 rev. e | page 18 of 32 tability the i-to-v configuration, the i out of the dac and the verting node of the op amp must be connected as close as roper pcb layout techniques must be employed. , gain at the output, and too e he voltage-switching d to the i out 1 pin, and t the v ref terminal. in this he s in in possible, and p because every code change corresponds to a step function peaking may occur if the op amp has limited gain bandwidth product (gbp) and there is excessive parasitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in the closed-loop applications circuit. an optional compensation capacitor, c1, can be added in parallel with r fb for stability, as shown in figure 44 and figure 45 . too small a value of c1 can produce ringing large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for th compensation. single-supply applications voltage-switching mode figure 46 shows these dacs operating in t mode. the reference voltage, v in , is applie the output voltage is available a configuration, a positive reference voltage results in a positive output voltage, making single-supply operation possible. the output from the dac is voltage at a constant impedance (t dac ladder resistance); therefore, an op amp is necessary to buffer the output voltage. the reference input no longer sees constant input impedance, but one that varies with code; therefore, the voltage input should be driven from a low impedance source. 0 4587-011 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. r fb v in i out 1v ref gnd v dd v dd v out r1 r2 figure 46. single-supply voltage-switching mode it is important to note that with this configuration v in is limited to low volta r d not have the same s heir on ositive output voltage he output voltage polarity is opposite to the v ref polarity for eference voltages. to achieve a positive voltage output, an the input of the dac is preferred tual ges because the switches in the dac ladde ource-drain drive voltage. as a result, t o resistance differs, which degrades the integral linearity of the dac. also, v in must not go negative by more than 0.3 v, or an internal diode turns on, causing the device to exceed the maximum ratings. in this type of application, the full range of multiplying capability of the dac is lost. p t dc r applied negative reference to over the output inversion through an inverting amplifier because of the resistors tolerance errors. to generate a negative reference, the reference can be level-shifted by an op amp such that the v out and gnd pins of the reference become the vir ground and ?2.5 v, respectively, as shown in figure 47 . 04587-012 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. r fb i out 1 gnd ?5v +5v adr03 gnd v out v in v dd = +5v v ref ?2.5v c1 v dd v out = 0v to +2.5v figure 47. positive output voltage with minimum components adding gain in ap greater than v in , gain can be added with an additional external e achieved in a single stage. it is important t d 1 plications in which the output voltage is required to be amplifier, or it can b to consider the effect of the temperature coefficients of the dacs thin film resistors. simply placing a resistor in series with the r fb resistor causes mismatches in the temperature coefficients and results in larger gain temperature coefficien errors. instead, increase the gain of the circuit by using the recommended configuration shown in figure 48 . r1, r2, an r3 should have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains greater than are required. 04587-013 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. r fb i out 1 gnd r1 v ref v in v dd v dd c1 v out r3 r2 gain = r2 + r3 r2 r1 = r2r3 r2 + r3 figure 48. increasing gain of current-output dac
ad5450/ad5451/ad5452/ad5453 rev. e | page 19 of 32 ivider or programmable gain element urrent-steering dacs are very flexible and lend themselves to ny different applications. if this type of dac is connected as ut d c ma the feedback element of an op amp and r fb is used as the inp resistor as shown in figure 49 , the output voltage is inversely proportional to the digital input fraction, d. for d = 1 ? 2 ? n , the output voltage is () n in in out vv v ? ? = ? = d ? 21 as d is reduced, the output voltage increases. for small values of the digital fraction, d, it is important to ensure that the amplifier does not saturate and that the required accuracy is e 49 met. for example, an 8-bit dac driven with the binary code 0x10 (00010000), that is, 16 decimal, in the circuit of figur should cause the output voltage to be 16 times v in . 0 4587-014 note a dditional pins omitted for clarit y r fb i out 1v ref gnd v dd v dd v out v in figure 49. current-steering dac used as a divider or programmable gain element however, if the dac has a linearity specification o 0.5 lsb, d can have w .5/256. therefore, the poss ange of 15.5 v in rom the op amp through the dac. : for eference selection use with this series of current- o 2 lsb accuracy requires a maximum . he current-steering mode is an e. he . portant in voltage- t r when selecting a reference for output dacs, pay attention to the references output voltage temperature coefficient specification. this parameter not only affects the full-scale error, but also may affect the linearity (inl and dnl) performance. the reference temperature coefficient should be consistent with the system accuracy specifications. for example, an 8-bit system is required to hold its overall specification to within 1 lsb over the temperature range 0c t 50c, and the systems maximum temperature drift should be less than 78 ppm/c. a 12-bit system within drift of 10 ppm/c. choosing a precision reference with a low output temperature coefficient minimizes this error source. table 7 lists some dc references available from analog devices that are suitable for use with this range of current-output dacs amplifier selection the primary requirement for t amplifier with low input bias currents and low input offset voltag the input offset voltage of an op amp is multiplied by the variable gain of the circuit due to the code-dependent output resistance of the dac. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the offset voltage of the amplifiers input. this output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which if large enough, could cause the dac to be nonmonotonic. the input bias current of an op amp generates an offset at t voltage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent significant errors in 12-bit applications however, for 14-bit applications, some consideration should be given to selecting an appropriate amplifier. common-mode rejection of the op amp is im f eight anywhere in the range of 15.5/256 to 16 ible output voltage is in the r to 16.5 v in an error of 3%, even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an opposite current supplied f switching circuits because it produces a code-dependent error at the voltage output of the circuit. most op amps have adequate common-mode rejection for use at 8-, 10-, and 12-bit resolutions. provided that the dac switches are driven from true wideband because only a fraction, d, of the current in the v ref terminal is routed to the i out 1 terminal, the output voltage changes as follows output error voltage dueto leakage = ( leakage r )/ d where r is the dac resistance at the v ref terminal. low impedance sources (v in and agnd), they settle quickly. consequently, the slew rate and settling time of a voltage- switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, i is important to minimize capacitance at the v ref node (the voltage output node in this application) of the dac. this is done by using low input-capacitance buffer amplifiers and careful board design. most single-supply circuits include ground as part of the analog a dac leakage current of 10 na, r = 10 k, and a gain (that is, 1/d) of 16, the error voltage is 1.6 mv. signal range, which in turn requires an amplifier that can handle rail-to-rail signals. there is a large range of single-supply amplifiers available from analog devices.
ad5450/ad5451/ad5452/ad5453 rev. e | page 20 of 32 n references part no. output voltage (v) initial tolerance (%) temp drift (ppm/c) i ss (ma) output noise (v p-p) package table 7. suitable adi precisio adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot-23, sc70 adr02 5 0.06 3 1 10 soic-8 adr02 5 0.06 9 1 10 tsot-23, sc70 adr03 2.5 0.10 3 1 6 soic-8 adr03 2.5 0.10 9 1 6 tsot-23, sc70 adr06 3 0.10 3 1 10 soic-8 adr06 3 0.10 9 1 10 tsot-23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic-8 adr435 5 0.04 3 0.8 8 soic-8 adr391 2.5 0.16 9 0.12 5 tsot-23 adr395 5 0.10 9 0.12 8 tsot-23 table 8. suitable adi precision op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) 0.1 hz to 10 hz noise (v p-p) supply current (a) package op97 2 to 20 25 0.1 0.5 600 soic-8 op1177 2.5 to 15 60 2 0.4 500 msop, soic-8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic-8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic-8 table 9. suitable adi high speed op amps part no. supply voltage (v) bw @ acl (mhz) slew rate (v/s) vos (max) (v) i b (max) (na) package ad8065 5 to 24 145 180 1500 0.006 soic-8, sot-23, msop ad8021 2.5 to 12 490 120 1000 10500 soic-8, msop ad8038 3 to 12 350 425 3000 750 soic-8, sc70-5 ad9631 3 to 6 320 1300 10000 7000 soic-8
ad5450/ad5451/ad5452/ad5453 rev. e | page 21 of 32 45 d us ter that is compatible w i, qspi, microw terface standards. d itten to the devic ord his 16-bit word cons f two control bits an , 14 a bits, as shown in fig , figure 51 , figure re es al ts of dac data, the us bits and ignores th lsbs, the ad5451 bits and ignores the four ls he ad5450 use d i res the six lsbs. t bits c1, c0 its c1 and c0 allow the u load and update th c e and to change the a lock edge. by defa e shift register clocks data upon the falling edge; this can be ac core is wer recycle is o r he fallin ower c o . o n r ns device pow n with zero sc th d i out l . d rol bits n implemented serial interface the ad5 0/ad5451/ad5452/a 5453 have an easy-to- e 3-wire in face ith sp ire, and most d sp in ata is wr e in 16-bit w s. t ists o d 8 10, 12, or dat ure 50 52 , and figu 53 . the ad5453 us l 14 bi ad5452 es 12 e two uses 10 bs, and t s 8 bits an gno dac con rol control b ser to e new dac od ctive c ult, th changed via the control bits. if changed, the d inoperative until the next data frame, and a po required t resets the c eturn it to active on t re to default condition g edge. a p n-chip power-o ycle eset circuitr y e loaded to ures that th e e dac register an ers o ale ine. table 10 ac cont c1 c0 functio 0 0 load and update (power-on default) 0 1 reserved 1 0 reserved 1 1 clock data to shift reg is ter upon rising edge sync function sync is a n e ered input tha s a frame- izat and chip enab ta can only be ansferred to the device while sync dge-trigg t acts a synchron ion signal le. da tr is low. to start the serial data transfer, sync should be taken low, observing the inimum sync m falling to sclk falling edge setup time, t 4 . to inimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, pon the falling edge of sync m u . the sclk and sdin input uffers are powered down upon the rising edge of sync b . fter the falling edge of the 16 th sclk pulse, bring sync a high to transfer data from the input shift register to the dac register. the serial interface to the ad5450 uses a 16-bit shift register. to m th latched to up te the da utput. for example ? loadin x3fff (a plete data sequence) the out to 10 v ll scale). ? user in ds to wri 0x3200 but after 12 act sync take care avoid inco plete data sequences as ese will be da c o , g 0 com will update put (fu ten te ive edges g h (in plete write sequence actually te the owing code: 0xf200. ? the user expects an tput of 5.6 v. howeve c oes hig com ). this w ill up da foll o u r, if syn goes hig r 12 va id clock edges then an i data seq f 12 bits is loaded. to complet t register t m the previous sequence en and used as the 4 msbs missing. the addition of these 4 bits will put the part in rising edge mode and the output o change. figure 54 , figure 55 , and table 11 ta fram ote that if more t 6-bits are loaded to th efore c h afte l ncomplete if uence o he 4 lsbs f e the sh are tak ro will show n show the da es for this example. also n hen 1 e part b syn goes high the las its will be latched. t 16-b 04587-005 db0 (lsb) db15 (msb) c1 c0 xxx db7 db6 db5 db4 db2 db0db1 xxx db3 control bits data bits figure 50. ad5450 8-bit input shift register contents db15 (msb) 04587-006 db0 (lsb) d db2 db1 c1 db7 db6 db8 x b5 db4 db3 db0 xxx c0 db9 control bits data bits e 51. ad5451 put shift re figur 10-bit in gister contents 04587-007 db0 (lsb) db15 (msb) db7 db6 db5 db4 db3 db2 db0 db1 c1 c0 db11 db10 db8 db9 xx control bits data bits figure 52. ad5452 12-bit input shift register contents 04587-008 db0 (lsb) db15 (msb) db9 db8 db7 db6 db5 db4 db2 db3 c1 c0 db13 db12 db10 db11 db0 db1 control bits data bits figure 53. ad5453 14-bit input shift register contents 04587-054 111 1 11 1 1 00 11 1 1 1 1 control bits data bits figure 54. ad5453 first write, complete data sequence (0x3fff)
ad5450/ad5451/ad5452/ad5453 rev. e | page 22 of 32 04587-055 1 000 00 00 11 11 0 0 0 0 control bits data bits 1000 00 00 00 11 0 0 0 0 control bits intended data frame actual data frame data bits qu ence ( 20 data transf to the device figure 55. ad5453 second write, incomplete data se table 11. writing sequence data write in shift register action expected 0x3 0) and subsequent additional bits (0xf200) er action carried out 1 0x3fff load and update 0x3fff 0x3fff load and update 0x3fff 2 0x3200 load and update 0x3200 0xf200 ) clock data to shift register upon rising edge (0xf200 microprocessor interfacing microprocessor interfacing to a ad5450/ad5451/ad5452/ ad5453 dac is through a serial bus that uses standard protocol and is compatible with microcontrollers and dsp processors. the communication channel is a 3-wire interface consisting a clock signal, a data signal, and a synchro of nization signal. the 5453 require a 16-bit word, with def b lling edge of sclk, but nge -word. sp xx 0/ad5451/ad5452/ad5453 terf e mily of dsps is easily interfaced to a ad5450/ ad5453 dac without the need for extra glue he dac ine, ad5450/ad5451/ad5452/ad the ault eing data valid upon the fa this is cha able using the control bits in the data ad -21 -to-ad545 in ac the adsp-21xx fa ad5451/ad5452/ logic. figure 56 is an example of an spi interface between t and the adsp-2191m. sck of the dsp drives the serial data l sdin. sync is driven from one of the port lines, in this case spixsel . sclk sck sync spixsel sdin mosi adsp-2191* *additional pins omitted for clarity ad5450/ad5451/ ad5452/ad5453* 04587-100 figure 56. adsp-2191 spi-to-ad5450/ad5451/ad5452/ad5453 interface a serial interface between the dac and dsp sport is shown in figure 57 . in this example, sport0 is used to transfer data to the dac shift register. transmission is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out upon each rising edge of the dsps serial clock and clocked into the dac input shift register upon the falling edge of its scl. the update of the dac output takes place upon the rising edge of the snc signal. sclk sclk sync tfs sdin dt ad ad ad *additional pins omitted for clarity sp-2101/ sp-2103/ sp-2191* ad5450/ad5451/ ad5452/ad5453* 04587-051 figure 57. adsp-2101/adsp-2103/adsp-2191 sport-to-ad5450/ad5451/ad5452/ad5453 interface communi peed is ossible when the following specifications are compatible ame snc cation between two devices at a given clock s p fr delay and frame snc setup-and-hold, data delay and data setup-and-hold, and scl width. the dac interface expects a t 4 ( snc falling edge to scl falling edge setup time) of 13 ns minimum. see the adsp-21xx user manual for infor- mation o n clock and frame snc frequencies for the sp ort gister. table 1 2 shows the setup for the sport control register. table 12. sport control register setup name setting description re tfsw 1 alternate framing invtfs 1 active low frame signal dtype 00 right justify data is clk 1 internal serial clock tfsr 1 frame every word itfs 1 internal framing signal slen 1111 16-bit data-word adsp-bf5xx-to-ad5450/ad5451/ad5452 interface he adsp-bf5xx family of processors has an spi-compatible port that enables the processor to communicate with spi- compatible devices. a serial interface between the blackfin ? processor and the ad5450/ad5451/ad5452/ad5453 dac is shown in figure 58 . in this configuration data is transferred thro /ad5453 t ugh the mosi (master output slave input) pin. snc is driven by the spixsel pin which is a reconfigured programmable flag pin.
ad5450/ad5451/ad5452/ad5453 rev. e | page 23 of 32 sclk sck sync spixsel sdin mosi adsp-bf5xx* *additional pins omitted for clarity ad5450/ad5451/ ad5452/ad5453* 04587-1 8. ad 0/ ad5451/ad5452/ad5453 interface e adsp-bf essor inco ou serial ports (sport). a serial interface between the dac and dsp spor n in figu enabled, initiate transmission by writing a word to the tx gister. the data is clocked out upon each rising edge of the sps serial clock and clocked into the dacs input shift dac output is ne 02 figure 5 sp-bf5xx-to-ad545 th 5xx proc rporates channel synchron s the t is show re 59 . when the sport is re d register upon the falling edge its sclk. the updated by using the transmit frame synchronization (tfs) li to provide a sync signal. sclk sclk sync tfs sdin dt adsp-bf5xx* *additional pins omitted for clarity 04587-103 sp-bf5xx sport-to-ad5450/ad5451/ad5452/ad5453 interface is a bit-programmable pin on the serial port and is used to drive sync ad5450/ad5451/ ad5452/ad5453* figure 59. ad 80c51/80l51-to-ad5450/ad5451/ad5452/ad5453 interface a serial interface between the dac and the 80c51/80l51 is shown in figure 60 . txd of the 80c51/80l51 drives sclk of the dac serial interface, and rxd drives the serial data line, sdin. p1.1 . as data is transmitted to the switch, p1.1 is taken low. the 80c51/80l51 transmit data only in 8-bit bytes; there- fore, only eight falling clock edges occur in the transmit cycle. to load data correctly to the dac, p1.1 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. data on rxd is clocked out of the microcontroller upon the rising edge of txd and is valid upon th g . e falling edge. as a result, no glue logic is required between the dac and microcontroller interface. p1.1 is taken high followin the completion of this cycle. the 80c51/80l51 provide the lsb of its sbuf register as the first bit in the data stream. the dac input register acquires its data with the msb as the first bit received the transmit routine should take this into account. sclk txd 8051* sync p1.1 sdin rxd *additional pins omitted for clarity 04587-104 ad5450/ad5451/ ad5452/ad5453* figure 60. 80c51/80l51-to-ad5450/ad5451/ad5452/ad5453 interface c68hc 451/ad5452/ad5453 interfac figure 61 is an example of a serial interface between the dac and the m interface (spi) on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, and clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr); see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the dac interface; the mosi output drives the serial data line (sdin) of the dac. the sync m 11-to-ad5450/ad5 e c68hc11 microcontroller. the serial peripheral signal is derived from a port line (pc7). when data is being transmitted to the ad5450/ad5451/ad5452/ad5453, the sync line is taken low (pc7). data appearing on the mosi output is valid upon the falling edge of sck. serial data from the 68hc11 is clock transmitted in 8-bit bytes with only eight falling edges occurring in the transmit cycle. data is transmitted msb first. to load data to the dac, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. sclk sck ad5450/ad5451/ ad5452/ad5453* sync pc7 sdin mosi mc68hc11* *additio nal pin for cl s omitted arity 04587-105 re 61. m hc11-to-ad54 d5453 interface er wa o verify th to the ift reg , the sdo l d to miso of 68hc in this conf figu c68 50/ad5451/ad5452/a if the us nts t e data previously written input sh ister ine can be connec te iguration with the mc 11. sync low, the shift er clocks ta out upon t regis t da he rising edges of sclk.
ad5450/ad5451/ad5452/ad5453 rev. e | page 24 of 32 microwire-to-ad5450/ ad5451/ad5452/ad5453 interface figure 62 shows an interface between the dac and any microwire-compatible device. serial data is shifted out upon the falling edge of the serial clock, sk, and is clocked into the dac input shift register upon the rising edge of sk, which corresponds to the falling edge of the dacs sclk. sclk sk microwire* sync cs sdin so ad5450/ad5451/ ad5452/ad5453* *additional pins omitted for clarity 04587-106 e 2/ad5453 interface the pic16c6x/pic16c7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon); see the pic16/pic17 microcontroller user manual . in this example, i/o port ra1 is used to provide a sync figure 62. microwire-to-ad5450/ad5451/ad5452/ad5453 interfac pic16c6x/pic16c7x-to- ad5450/ad5451/ad545 signal and enable the serial port of the dac. this microcontroller operation; therefore, two consecutive write operations are 045 pcb laout and power suppl decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which a ad5450/ad5451/ad5452/ad5453 dac is mounted should be designed so that the analog and digital sections are separated an system where multiple devices require an agnd-to-dgnd only. und point should be established as close as possible age al logic ls ite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is the best solution, but its use is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane and signal traces are placed on the solder side. it i pcb layout design. leads to the input should be as short as lose to the device as possible. d confined to certain areas of the board. if the dac is in a connection, the connection should be made at one point the star gro to the device. these dacs should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the pack as possible, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to intern switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. components, such as clocks, that produce fast switching signa should be shielded with a digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on oppos transfers only eight bits of data during each serial transfer required. figure 63 shows the connection diagram. sclk sck/rc3 pic16c6x/pic16c7x* sync ra1 sdin sdi/rc4 ad5450/ad5451/ ad5452/ad5453* *additional pins omitted for clarity 87-107 figure 63. pic16c6x/7x-to-ad5450/ad5451/ad5452/ad5453 interface s good practice to employ compact, minimum lead length possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to optimize high frequency performance, the i-to-v amplifier should be located as c
ad5450/ad5451/ad5452/ad5453 rev. e | page 25 of 32 d5452, an the evaluation kit consists of a cd with pc software to control the dac. the software allows the user to write code to the device. evaluation board for the dac the evaluation board consists of an ad5450, ad5451, a or ad5453 dac and a current-to-voltage amplifier, such as ad8065. included on the evaluation board is a 10 v reference, adr01. an external reference can also be applied via an smb input. power supplies for the evaluation board the board requires 12 v and +5 v supplies. the +12 v v dd and ?12 v v ss are used to power the output amplifier; the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors. v ss c7 10f + c7 0.1f v dd c9 10f + c10 0.1f p1?19 p1?20 p1?21 p1?22 p1?23 p1?24 p1?25 p1?26 p1?27 p1?28 p1?29 p1?30 p1?3 sclk j3 v out j1 p1?2 sdin j4 p1?4 sync j5 r1 v dd 1 10k sclk sdin sync 6 sclk ad5450/ ad5451/ ad5452/ 3 u1 3 v dd 5 sdin 4 sync ad545 1 r fb 8 i out 1 7 gnd 2 v ref c1 0.1f c2 10f + v dd 1 v? v+ u3 ad8065ar 2 3 6 4 7 c6 1.8pf tp c5 0.1f c4 0.1f + lk1 v ref j2 v ref c3 10f 3 v in 4 v out 5 trim 1 u2 gnd 2 v dd c11 0.1f c12 10f + c13 v dd p2?3 p2?2 0.1f c14 + 10f v ss agnd c15 0.1f v dd 1 p2?4 c16 10f + p2?1 04 587-056 figure 64. schematic of ad5450/ad5451/a d5452/ad5453 evaluation board
ad5450/ad5451/ad5452/ad5453 rev. e | page 26 of 32 04587-057 figure 65. component-side artwork 04587-058 figure 66. silkscreencomponent-side view (top)
ad5450/ad5451/ad5452/ad5453 rev. e | page 27 of 32 04587-059 figure 67. solder-side artwork table 13. overview of ad54xx and ad55xx devices art no. resolution no. dacs inl (lsb) interface package 1 features p ad5424 8 1 0.25 para llel ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial uj-8 12 mhz bw, 50 mhz serial interface ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 para llel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial uj-8 12 mhz bw, 50 mhz serial interface ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-10 12 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru-24 10 mhz bw, 50 mhz serial ad5405 12 2 1 parallel cp-40 10 mhz bw, 17 ns cs pulse width ad5445 12 2 1 para llel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial uj-8, rm-8 12 mhz bw, 50 mhz serial interface ad5446 14 1 1 serial rm-10 12 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 12 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 4 mhz bw, 50 mhz serial clock 1 serial rm-8 a d5557 14 2 1 parallel ru-38 4 mhz bw, 20 ns wr pulse width ad5 543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock a d5546 16 1 2 parallel ru-28 4 mhz bw, 20 n wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru-38 4 mhz bw, 20 ns wr pulse width 1 ru = tssop, cp = lfcsp, rm = msop, uj = tsot.
ad5450/ad5451/ad5452/ad5453 rev. e | page 28 of 32 outline dimensions 13 56 2 8 4 7 2.90 bsc pin 1 indicator 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.10 max * 0.90 0.87 0.84 seating plane * 1.00 max 0.20 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc * compliant to jedec standards mo-193-ba with the exception of package height and thickness. compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 68. 8-lead thin small outline transistor package [tsot] (uj-8) dimensions shown in millimeters figure 69. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0228 08-b top vi ew 8 1 5 4 0.35 0.30 0.25 * exposed pad (bottom vie pin 1 index area 3.00 bsc s w) q seating plane 0.80 0.75 0.70 0.20 ref 0. 0. 05 max 02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0. 0. 0. 50 40 30 0.65 bsc p i n 1 i n d i c a t o r ( r 0 . 2 ) * fo r proper c n of th lease e pin conf u scriptions s this data figur ad lea scale p_wd] 3 mm ery very th -8-3) dimen wn in mill onnectio e exposed pad p refer to th of iguration and f sheet. nction de ection e 70. 8-le d frame chip package [lfcs 3 mm body, v in, dual lead (cp sions sho imeters
ad5450/ad5451/ad5452/ad5453 rev. e | page 29 of 32 n inl temperature range package description package option branding ordering guide model 1 , 2 resolutio a d5450yujz-reel 8 0.25 ?40c to +125c 8-lead tsot uj-8 d6y ad5450yujz-reel7 8 0.25 ?40c to +125c 8-lead tsot uj-8 d6y ad5451yujz-reel 10 0.25 ?40c to +125c 8-lead tsot uj-8 d6z ad5451yujz-reel7 10 0.25 ?40c to +125c 8-lead tsot uj-8 d6z AD5452YUJZ-REEL 12 0.5 ?40c to +125c 8-lead tsot uj-8 d70 AD5452YUJZ-REEL7 12 0.5 ?40c to +125c 8-lead tsot uj-8 d70 ad5452yrm 12 0.5 ?40c to +125c 8-lead msop rm-8 d1z ad5452yrm-reel 12 0.5 ?40c to +125c 8-lead msop rm-8 d1z ad5452yrmz 12 0.5 ?40c to +125c 8-lead msop rm-8 d70 ad5452yrmz-reel 12 0.5 ?40c to +125c 8-lead msop rm-8 d70 ad5452yrmz-reel7 12 0.5 ?40c to +125c 8-lead msop rm-8 d70 ad5453wbcpz-rl 14 2 ?40c to +125c 8-lead lfcsp_wd cp-8-3 dg3 ad5453yujz-reel 14 2 ?40c to +125c 8-lead tsot uj-8 dah ad5453yujz-reel7 14 2 ?40c to +125c 8-lead tsot uj-8 dah ad5453yrm 14 2 ?40c to +125c 8-lead msop rm-8 d26 ad5453yrm-reel 14 2 ?40c to +125c 8-lead msop rm-8 d26 ad54 +125c 8-lead msop 53yrm-reel7 14 2 ?40c to rm-8 d26 ad5453yrmz 14 2 ?40c to +125c 8-lead msop rm-8 dah ad5453yrmz-ree ?40c to +125c 8-lead msop dah l 14 2 rm-8 ad5453y rmz-reel7 14 2 ?40c to +125c 8-lead msop rm-8 dah e val-ad5451ebz evaluation kit eval-ad5452ebz evaluation kit eval-ad5453ebz evaluation kit 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the ad5453wbcpz-rl model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that this automotive model may have specifications that differ from the commercial models; theref ore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are a vailable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for these models.
ad5450/ad5451/ad5452/ad5453 rev. e | page 30 of 32 notes
ad5450/ad5451/ad5452/ad5453 rev. e | page 31 of 32 notes
ad5450/ad5451/ad5452/ad5453 rev. e | page 32 of 32 ?2005C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04587-0-3/11(e) notes

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